Among the critical issues for a conventional DRAM, ratio of bit line capacitance to cell capacitance, if not well controlled, deleteriously affects the initial charge sharing time to generate the required differential signal for proper sensing. Also, in a conventional DRAM, a data bit `one` requires longer time to restore, thereby undesirably lengthening the write cycle time. Additionally, cell leakage affecting the stored `one,` which can hurt production ramp-up. Furthermore, even though DRAM is better than static random access memory (SRAM) in terms of available density and structural simplicity, SRAM is still better than DRAM in term of data access speed.
Thus, a need exists for an improved DRAM that offers the size advantage of DRAM without sacrificing the speed. That is, a need exists for an improved DRAM that decreases the gap between its speed and SRAM's speed. Additionally, a need exists for an improved DRAM that does not have bad ratio of BL capacitance to cell capacitance. Furthermore, a need exists for an improved DRAM that is not difficult to control the initial charge sharing time to generate the required differential for proper sensing. Further still, a need exists for an improved DRAM that does not have problem with cell leakage that affects the stored `one` and hurts production ramp-up.